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DS024 (v1.7) august 21, 2003 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features low power 3.3v 384 macrocell cpld 7.5 ns pin-to-pin logic delays system frequencies up to 135 mhz 384 macrocells with 9,000 usable gates available in small footprint packages - 144-pin tqfp (118 user i/o) - 208-pin pqfp (172 user i/o) - 256-ball fbga (212 user i/o) - 324-ball fbga (220 user i/o) optimized for 3.3v systems - ultra low power operation - 5v tolerant i/o pins with 3.3v core supply - advanced 0.35 micron five layer metal eeprom process - fast zero power? (fzp) cmos design technology - 3.3v pci electrical specification compatible outputs (no internal clamp diode on any input or i/o) advanced system features - in-system programming - input registers - predictable timing model - up to 23 clocks available per function block - excellent pin retention during design changes - full ieee standard 1149.1 boundary-scan (jtag) - four global clocks - eight product term control terms per function block fast isp programming times port enable pin for additional i/o 2.7v to 3.6v supply voltage at industrial grade voltage range programmable slew rate control per output security bit prevents unauthorized access refer to xpla3 family data sheet ( ds012 ) for architecture description description the xcr3384xl is a 3.3v, 384 macrocell cpld targeted at power sensitive designs that require leading edge program- mable logic solutions. a total of 24 function blocks provide 9,000 usable gates. pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 135 mhz. totalcmos design technique for fast zero power xilinx offers a totalcmos cpld, both in process technol- ogy and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate imple- mentation allows xilinx to offer cplds that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 1 and ta ble 1 showing the i cc vs. frequency of our xcr3384xl totalcmos cpld (data taken with 24 resetable up/down, 16-bit counters at 3.3v, 25c). 0 xcr3384xl: 384 macrocell cpld DS024 (v1.7) august 21, 2003 014 preliminary product specification r figure 1: xcr3384xl typical i cc vs. frequency at v cc = 3.3v, 25 c 0 40 80 120 160 200 240 280 0 20 40 60 80 100 120 140 DS024_01_061802 frequency (mhz) typical i cc (ma) table 1: typical i cc vs. frequency at v cc = 3.3v, 25 c frequency (mhz) 0 1 10 20 40 60 80 100 120 140 ty p i c a l i cc (ma) 0.02 2.2 24.4 42.4 82.6 123.0 155.6 187.8 227.5 258.1
xcr3384xl: 384 macrocell cpld 2 www.xilinx.com DS024 (v1.7) august 21, 2003 1-800-255-7778 preliminary product specification r dc electrical characteristics over recommended operating conditions (1) symbol parameter test conditions min. max. unit v oh ( 2 ) output high voltage v cc = 3.0v to 3.6v, i oh = ?8 ma 2.4 - v v cc = 2.7v to 3.0v, i oh = ?8 ma 2.0 - v i oh = ?500 a 90% v cc ( 3 ) -v v ol output low voltage i ol = 8 ma - 0.4 v i il input leakage current v in = gnd or v cc to 5.5v ?10 10 a i ih i/o high-z leakage current v in = gnd or v cc to 5.5v ?10 10 a i ccsb standby current v cc = 3.6v - 100 a i cc dynamic current ( 4 , 5 ) f = 1 mhz - 5 ma f = 50 mhz - 140 ma c in input pin capacitance ( 6 ) f = 1 mhz - 8 pf c clk clock input capacitance ( 6 ) f = 1 mhz - 12 pf c i/o i/o pin capacitance ( 6 ) f = 1 mhz - 10 pf notes: 1. see xpla3 family data sheet ( ds012 ) for recommended operating conditions 2. see figure 2 for output drive characteristics of the xpla3 family. 3. this parameter guaranteed by design and characterization, not by testing. 4. see table 1 , figure 1 for typical values. 5. this parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 6. typical values, not tested. figure 2: typical i/v curve for the xpla3 family, 25c 0 0 1 0 2 0 30 4 0 50 60 7 0 80 90 1 00 0 . 5 1 1. 5 2 2. 5 3 3 . 5 4 4. 5 5 volt s i o l ( 3.3v ) i o h ( 3.3v ) i o h ( 2.7v ) ma ds012 _ 10 _ 03180 2
xcr3384xl: 384 macrocell cpld DS024 (v1.7) august 21, 2003 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r ac electrical characteristics over recommended operating conditions (1,2) symbol parameter -7 -10 -12 unit min. max. min. max. min. max. t pd1 propagation delay time (single p-term) - 7.0 - 9.0 - 10.8 ns t pd2 propagation delay time (or array) (3) - 7.5 - 10.0 - 12.0 ns t co clock to output (global synchronous pin clock) - 4.5 - 5.8 - 6.9 ns t suf setup time(fast input register) 2.5 - 3.0 - 3.0 - ns t su1 (4) setup time (single p-term) 4.3 - 5.5 - 6.7 - ns t su2 setup time (or array) 4.8 - 6.5 - 7.9 - ns t h (4) hold time 0-0-0-ns t wlh (4) global clock pulse width (high or low) 3.0 - 4.0 - 5.0 - ns tt plh (4) p-term clock pulse width 4.5 - 6.0 - 7.5 - ns t r (4) input rise time - 20 - 20 - 20 ns t l (4) input fall time - 20 - 20 - 20 ns f system (4) maximum system frequency - 135 - 102 - 83 mhz t config (4) configuration time (5) - 200 - 200 - 200 s t init (4) isp initialization time - 200 - 200 - 200 s t poe (4) p-term oe to output enabled - 9.0 - 11.0 - 13.0 ns t pod (4) p-term oe to output disabled (6) - 9.0 - 11.0 - 13.0 ns t pco (4) p-term clock to output - 8.0 - 10.3 - 12.4 ns t pao (4) p-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns notes: 1. specifications measured with one output switching. 2. see xpla3 family data sheet ( ds012 ) for recommended operating conditions. 3. see figure 4 for derating. 4. these parameters guaranteed by design and/or characterization, not testing. 5. typical current draw during configuration is 13 ma at 3.6v. 6. output c l = 5 pf.
xcr3384xl: 384 macrocell cpld 4 www.xilinx.com DS024 (v1.7) august 21, 2003 1-800-255-7778 preliminary product specification r internal timing parameters (1,2) symbol parameter -7 -10 -12 unit min. max. min. max. min. max. buffer delays t in input buffer delay - 2.5 - 3.3 - 4.0 ns t fin fast input buffer delay - 2.7 - 3.3 - 3.3 ns t gck global clock buffer delay - 1.0 - 1.3 - 1.5 ns t out output buffer delay - 2.5 - 3.2 - 3.8 ns t en output buffer enable/disable delay - 4.5 - 5.2 - 6.0 ns internal register and combinatorial delays t ldi latch transparent delay - 1.3 - 1.6 - 2.0 ns t sui register setup time 0.8 - 1.0 - 1.2 - ns t hi register hold time 0.3 - 0.5 - 0.7 - ns t ecsu register clock enable setup time 2.0 - 2.5 - 3.0 - ns t echo register clock enable hold time 3.0 - 4.5 - 5.5 - ns t coi register clock to output delay - 1.0 - 1.3 - 1.6 ns t aoi register async. s/r to output delay - 2.0 - 2.0 - 2.2 ns t rai register async. recovery - 5.0 - 7.0 - 8.0 ns t ptck product term clock delay - 2.0 - 2.5 - 3.0 ns t logi1 internal logic delay (single p-term) - 2.0 - 2.5 - 3.0 ns t logi2 internal logic delay (pla or term) - 2.5 - 3.5 - 4.2 ns feedback delays t f zia delay - 3.1 - 4.0 - 5.0 ns time adders t logi3 fold-back nand delay - 2.0 - 2.5 - 3.0 ns t uda universal delay - 2.2 - 2.8 - 3.5 ns t slew slew rate limited delay - 4.0 - 5.0 - 6.0 ns notes: 1. these parameters guaranteed by design and/or characterization, not testing. 2. see xpla3 family data sheet ( ds012 ) for timing model.
xcr3384xl: 384 macrocell cpld DS024 (v1.7) august 21, 2003 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r switching characteristics figure 3: ac load circuit ds023_03_102401 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t poe (high) t poe (low) t p open closed closed open closed closed v cc v out v in c1 r1 r2 s1 s2 note: for t pod , c1 = 5 pf. delay measured at output level of v ol + 300 mv, v oh ? 300 mv. figure 4: derating curve for t pd2 6.3 6.4 6.5 6.0 6.1 6.2 6.6 6.7 6.8 6.9 7.0 7.1 7.2 124816 DS024_04_061802 number of adjacent outputs switching 3.3v, 25 c (ns) figure 5: voltage waveform 90% 10% 1.5 ns 1.5 ns ds017_05_042800 +3.0v 0v measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. t r t l
xcr3384xl: 384 macrocell cpld 6 www.xilinx.com DS024 (v1.7) august 21, 2003 1-800-255-7778 preliminary product specification r pin descriptions table 2: xcr3384xl user i/o pins tq144 (1) pq208 ft256 fg324 to t a l u s e r i/o pins 118 172 212 220 notes: 1. xcr3384xl tq144 jtag pins are not compatible with other members of the xpla3 family in the tq144 package. table 3: xcr3384xl i/o pins function block macro- cell tq144 (1) pq208 ft256 fg324 1 1 94 - e15 g22 12- -f13h20 13-13e16h21 14-15f14j19 1 5 93 16 f15 j21 16- -- - 17- -- - 18- -- - 19- -- - 110- - - - 111- - - - 112- - - - 1139217g12j22 1 14 - 18 g15 k19 1 15 - 19 g13 k21 1169120f16k22 21-12e14g21 2 2 96 11 d16 g19 2 3 97 10 f12 f22 24989c16f21 2 5 99 8 e13 f20 26- -- - 27- -- - 28- -- - 29- -- - 210- - - - 211- - - - 212- - - - 2 13 100 - d15 e22 2 14 101 7 d14 e21 2 15 102 6 b16 f19 2 16 103 - c15 e20 3 1 - 21 g14 l19 32-22g16l20 33- -h13l21 3490--m20 3 5 89 24 h12 m19 36- -- - 37- -- - 38- -- - 39- -- - 310- - - - 311- - - - 312- - - - 3 13 - 25 h15 m22 3148826h14n22 3 15 - 27 h16 n21 3168728j14n19 411044a16d22 421063e12c22 43107--b21 44110-c14b20 4 5 111 207 d13 c19 46- -- - 47- -- - 48- -- - 49- -- - 410- - - - 411- - - - 412- - - - 4 13 112 206 a15 b19 4 14 113 205 b15 a20 4 15 114 204 b14 c18 4 16 116 203 c13 b18 51-29j15p22 5286 (1,2) 30 (2) j13 (2) p20 (2) 53-31j16p19 54- -l14r22 5 5 84 - k15 r21 56- -- - 57- -- - 58- -- - 59- -- - 510- - - - 511- - - - ta ble 3 : xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324
xcr3384xl: 384 macrocell cpld DS024 (v1.7) august 21, 2003 www.xilinx.com 7 preliminary product specification 1-800-255-7778 r 512- - - - 513- 33k14r20 5148334k16t22 5158235k13t21 5 16 81 36 l15 t20 616762r13aa16 62-61m11y16 63-60t14w16 6 4 - 59 n12 ab17 6 5 - 58 r14 aa17 66- -- - 67- -- - 68- -- - 69- -- - 610- - - - 611- - - - 612- - - - 613- 57p13ab18 614- 56t15aa18 61568 -p14w17 61669 -t16aa19 7 1 80 37 k12 t19 7 2 79 38 l16 u22 7 3 78 39 m15 u21 7 4 77 40 n15 u20 7 5 - - l13 v22 76- -- - 77- -- - 78- -- - 79- -- - 710- - - - 711- - - - 712- - - - 713- -m16u19 7 14 - 42 m14 v21 7157543n16v20 7 16 - 44 l12 w22 8 1 70 55 m12 y18 827151r15aa20 8372-n13y19 84- --aa21 85-49p16y20 table 3: xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324 86- -- - 87- -- - 88- -- - 89- -- - 810- - - - 811- - - - 812- - - - 8 13 - 48 n14 y21 8 14 - 47 r16 w20 8 15 - 46 m13 w21 8167445p15y22 9 1 122 187 d9 c13 9 2 - 188 a9 d13 9 3 121 (1,2) 189 (2) c10 (2) b14 (2) 9 4 - 190 a10 c14 95120-d10d14 96- -- - 97- -- - 98- -- - 99- -- - 910- - - - 911- - - - 912- - - - 913- -b11a15 9 14 - 192 c11 b15 9 15 - 193 b12 c15 9 16 - 194 e10 a16 10 1 - 178 b8 b11 10 2 - 177 d8 c11 10 3 131 (1,2) 176 (2) a7 (2) d11 (2) 10 4 132 175 c8 a10 10 5 - - - b10 10 6 - - - - 10 7 - - - - 10 8 - - - - 10 9 - - - - 10 10 - - - - 10 11 - - - - 10 12 - - - 10 13 - - c7 c10 10 14 - 173 b7 d10 10 15 133 172 d7 a9 ta ble 3 : xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324
xcr3384xl: 384 macrocell cpld 8 www.xilinx.com DS024 (v1.7) august 21, 2003 1-800-255-7778 preliminary product specification r 10 16 134 171 a6 b9 11 1 - - a14 a19 11 2 - 202 e11 d17 11 3 - 201 a13 a18 11 4 - - d12 c17 11 5 117 199 b13 b17 11 6 - - - - 11 7 - - - - 11 8 - - - - 11 9 - - - - 11 10 - - - - 11 11 - - - - 11 12 - - - - 11 13 - 198 c12 a17 11 14 - 197 a12 d16 11 15 118 196 d11 c16 11 16 119 195 a11 b16 12 1 139 163 e6 d7 12 2 - 164 a4 c7 12 3 138 - c5 b7 12 4 137 - b5 a7 12 5 - 166 d6 c8 12 6 - - - - 12 7 - - - - 12 8 - - - - 12 9 - - - - 12 10 - - - - 12 11 - - - - 12 12 - - - - 12 13 136 167 a5 b8 12 14 - 168 c6 a8 12 15 - 169 b6 d9 12 16 - 170 e7 c9 13 1 61 70 n10 w13 13 2 - 69 p11 ab14 13 3 62 68 m10 aa14 13 4 63 67 r11 y14 13 5 - 66 t12 w14 13 6 - - - - 13 7 - - - - 13 8 - - - - 13 9 - - - - table 3: xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324 13 10 - - - - 13 11 - - - - 13 12 - - - - 13 13 - 65 r12 ab15 13 14 65 64 n11 aa15 13 15 - - t13 y15 13 16 66 - p12 ab16 14 1 - 91 r6 aa8 14 2 47 92 m7 y8 14 3 46 93 t5 ab7 14 4 - - t6 aa7 14 5 - - r5 y7 14 6 - - - - 14 7 - - - - 14 8 - - - - 14 9 - - - - 14 10 - - - - 14 11 - - - - 14 12 - - - - 14 13 45 95 n6 w7 14 14 44 96 t4 ab6 14 15 - 97 p5 aa6 14 16 43 98 r4 y6 15 1 - - t11 y13 15 2 - - - aa13 15 3 60 71 r10 ab13 15 4 - 73 p10 w12 15 5 56 76 t10 aa12 15 6 - - - - 15 7 - - - - 15 8 - - - - 15 9 - - - - 15 10 - - - - 15 11 - - - - 15 12 - - - - 15 13 55 77 n9 ab12 15 14 - 78 r9 y11 15 15 - 79 p9 aa11 15 16 54 80 t9 w11 16 1 - 90 n7 ab8 16 2 48 89 t7 w9 16 3 - 88 p6 y9 ta ble 3 : xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324
xcr3384xl: 384 macrocell cpld DS024 (v1.7) august 21, 2003 www.xilinx.com 9 preliminary product specification 1-800-255-7778 r 16 4 49 87 r7 aa9 16 5 - 86 p7 ab9 16 6 - - - - 16 7 - - - - 16 8 - - - - 16 9 - - - - 16 10 - - - - 16 11 - - - - 16 12 - - - - 16 13 - - t8 w10 16 14 - - n8 y10 16 15 - 84 r8 aa10 16 16 53 81 p8 ab11 17 1 - 147 e4 e2 17 2 - 148 d1 f3 17 3 6 149 f5 f4 17 4 5 150 c2 d1 17 5 4 151 d3 d2 17 6 - - - - 17 7 - - - - 17 8 - - - - 17 9 - - - - 17 10 - - - - 17 11 - - - - 17 12 - - - - 17 13 - - c1 e3 17 14 - - - c2 17 15 2 153 b1 b2 17 16 1 154 b2 d3 18 1 7 146 d2 e1 18 2 8 145 e3 f2 18 3 9 144 e1 g4 18 4 10 - f4 g3 18 5 - - f1 g2 18 6 - - - - 18 7 - - - - 18 8 - - - - 18 9 - - - - 18 10 - - - - 18 11 - - - - 18 12 - - - - 18 13 - 142 g5 h3 table 3: xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324 18 14 - 141 e2 h2 18 15 11 140 f3 h1 18 16 12 139 f2 j4 19 1 - 155 c3 c4 19 2 143 156 d4 b4 19 3 - - a2 c5 19 4 142 - a1 b5 19 5 141 158 b3 a4 19 6 - - - - 19 7 - - - - 19 8 - - - - 19 9 - - - - 19 10 - - - - 19 11 - - - - 19 12 - - - - 19 13 - 159 c4 d6 19 14 - 160 a3 a5 19 15 140 161 d5 c6 19 16 - 162 b4 b6 20 1 14 138 g4 j3 20 2 - 137 g1 j2 20 3 - 136 g3 k4 20 4 15 135 h1 k3 20 5 - - h4 k2 20 6 - - - - 20 7 - - - - 20 8 - - - - 20 9 - - - - 20 10 - - - - 20 11 - - - - 20 12 - - - - 20 13 - - g2 k1 20 14 16 133 h3 l4 20 15 - 132 j1 l3 20 16 18 131 j3 l2 21 1 - 99 m6 ab5 21 2 - 100 t3 w6 21 3 42 101 n5 ab4 21 4 41 102 r3 aa5 21 5 - 103 p4 y5 21 6 - - - - 21 7 - - - - ta ble 3 : xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324
xcr3384xl: 384 macrocell cpld 10 www.xilinx.com DS024 (v1.7) august 21, 2003 1-800-255-7778 preliminary product specification r 21 8 - - - - 21 9 - - - - 21 10 - - - - 21 11 - - - - 21 12 - - - - 21 13 40 104 t2 aa4 21 14 39 - - ab3 21 15 38 - r2 y4 21 16 37 106 n4 aa3 22 1 19 - h2 m2 22 2 - 130 j5 m3 22 3 20 129 j2 m4 22 4 21 128 j4 n1 22 5 22 (1,2) 127 (2) k1 (2) n2 (2) 22 6 - - - - 22 7 - - - - 22 8 - - - - 22 9 - - - - 22 10 - - - - 22 11 - - - - 22 12 - - - - 22 13 23 126 k3 n3 22 14 - - - n4 22 15 - 124 k2 p1 22 16 25 123 l1 p2 23 1 36 108 m5 aa2 23 2 - 109 p2 y3 23 3 - 110 p3 y2 23 4 - 111 t1 w3 23 5 - - n3 w2 23 6 - - - - 23 7 - - - - 23 8 - - - - 23 9 - - - - 23 10 - - - - 23 11 - - - - 23 12 - - - - 23 13 - - r1 w1 23 14 35 112 m4 v3 23 15 - 113 p1 u4 23 16 - 114 l5 v2 24 1 26 122 k4 p3 table 3: xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324 24 2 27 121 l3 p4 24 3 28 120 k5 r1 24 4 29 119 m1 r2 24 5 30 - l2 r3 24 6 - - - - 24 7 - - - - 24 8 - - - - 24 9 - - - - 24 10 - - - - 24 11 - - - - 24 12 - - - - 24 13 31 118 m2 t2 24 14 32 117 l4 t3 24 15 - - m3 u2 24 16 34 115 n2 u3 notes: 1. xcr3384xl tq144 jtag pins are not compatible with other members of the xpla3 family in the tq144 package. 2. jtag pins. ta ble 3 : xcr3384xl i/o pins (continued) function block macro- cell tq144 (1) pq208 ft256 fg324
xcr3384xl: 384 macrocell cpld DS024 (v1.7) august 21, 2003 www.xilinx.com 11 preliminary product specification 1-800-255-7778 r table 4: xcr3384xl global, jtag, port enable, power, and no connect pins pin type tq144 (1) pq208 ft256 fg324 in0 / clk0 128 181 b9 c12 in1 / clk1 127 182 a8 b12 in2 / clk2 126 183 c9 d12 in3 / clk3 125 184 b10 a12 tck 86 (1) 30 j13 p20 tdi 131 (1) 176 a7 d11 tdo 121 (1) 189 c10 b14 tms 22 (1) 127 k1 n2 port_en 33 (2) 116 (2) n1 (2) t4 (2) v cc 24, 50, 51, 58, 73, 76, 95, 115, 123, 130, 144 5, 23, 41, 63, 74, 83, 85, 107, 125,143, 165, 179, 186, 191 e8, e9, f7, f8, f9, f10, g6, g11, h5, h6, h11, j6, j11, j12, k6, k11, l7, l8, l9, l10, m8, m9 a11, a13, d8, d15, h4, h19, j10, j11, j12, j13, k9, k14, l9, l14, m1, m9, m14, n9, n14, n20, p10, p11, p12, p13, r4, r19, w8, w15, y12, ab10 gnd 3, 13, 17, 52, 57, 59, 64, 85, 105, 124, 129, 135, 14, 32, 50, 72, 75, 82, 94, 134, 152, 174, 180, 185, 200 e5, f6, f11, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, l6, l11 d4, d5, d18, d19, e4, e19, j9, j14, k10, k11, k12, k13, l10, l11, l12, l13, m10, m11, m12, m13, n10, n11, n12, n13, p9, p14, v4, v19, w4, w5, w18, w19 no connects 108, 109 1, 2, 52, 53, 54, 105, 157, 208 - a1, a2, a3, a6, a14, a21, a22, b1, b3, b13, b22, c1, c3, c20, c21, d20, d21, f1, g1, g20, h22, j1, j20, k20, l1, l22, m21, p21, t1, u1, v1, y1, y17, aa1, aa22, ab1, ab2, ab19, ab20, ab21, ab22 notes: 1. xcr3384xl tq144 jtag pins are not compatible with other members of the xpla3 family in the tq144 package. 2. port enable is brought high to enable jtag pins when jtag pins are used as i/o. see family data sheet ( ds012) for full explanation.
xcr3384xl: 384 macrocell cpld 12 www.xilinx.com DS024 (v1.7) august 21, 2003 1-800-255-7778 preliminary product specification r device part marking and ordering combination information device ordering and part marking number speed (pin-to-pin delay) pkg. symbol no. of pins package type operating range (1) xcr3384xl-7tq144c 7.5 ns tq144 144-pin thin quad flat pack (tqfp) c xcr3384xl-7pq208c 7.5 ns pq208 208-pin plastic quad flat pack (pqfp) c xcr3384xl-7ft256c 7.5 ns ft256 256-ball fine-pitch bga (ft) c xcr3384xl-7fg324c 7.5 ns fg324 324-ball fineline bga package (fg) c xcr3384xl-10tq144c 10 ns tq144 144-pin thin quad flat pack (tqfp) c xcr3384xl-10pq208c 10 ns pq208 208-pin plastic quad flat pack (pqfp) c xcr3384xl-10ft256c 10 ns ft256 256-ball fine-pitch bga (ft) c xcr3384xl-10fg324c 10 ns fg324 324-ball fineline bga package (fg) c xcr3384xl-10tq144i 10 ns tq144 144-pin thin quad flat pack (tqfp) i xcr3384xl-10pq208i 10 ns pq208 208-pin plastic quad flat pack (pqfp) i xcr3384xl-10ft256i 10 ns ft256 256-ball fine-pitch bga (ft) i xcr3384xl-10fg324i 10 ns fg324 324-ball fineline bga package (fg) i xcr3384xl-12tq144c 12 ns tq144 144-pin thin quad flat pack (tqfp) c xcr3384xl-12pq208c 12 ns pq208 208-pin plastic quad flat pack (pqfp) c xcr3384xl-12ft256c 12 ns ft256 256-ball fine-pitch bga (ft) c xcr3384xl-12fg324c 12 ns fg324 324-ball fineline bga package (fg) c xcr3384xl-12tq144i 12 ns tq144 144-pin thin quad flat pack (tqfp) i xcr3384xl-12pq208i 12 ns pq208 208-pin plastic quad flat pack (pqfp) i xcr3384xl-12ft256i 12 ns ft256 256-ball fine-pitch bga (ft) i xcr3384xl-12fg324i 12 ns fg324 324-ball fineline bga package (fg) i notes: 1. c = commercial: t a = 0 to +70c; i = industrial: t a = ?40 to +85c xcrxxxxxl tq144 7c device type package speed operating range this line not related to device part number sample package with part marking. r 1
xcr3384xl: 384 macrocell cpld DS024 (v1.7) august 21, 2003 www.xilinx.com 13 preliminary product specification 1-800-255-7778 r revision history the following table shows the revision history for this document date version revision 02/08/01 1.0 initial xilinx release. 04/11/01 1.1 update tsuf spec to meet umc characterization data. added typical i/v curve, figure 2 ; added ta b l e 2 : total user i/o; changed v oh spec. added 324-ball fineline bga pinouts and package. 04/19/01 1.2 updated typical i/v curve, figure 2 : added voltage levels. 08/10/01 1.3 updated ac electrical characterisitics; internal timing parameters; added tq144 package and pinouts. 01/08/02 1.4 updated t suf spec to match software timing. added single p-term setup time (t su1 ) to ac table, renamed t su to t su2 for setup time through the or array. updated t init spec and t config spec. updated t hi spec to correct a typo. updated ac load circuit diagram to more closely resemble true test conditions, added note for t pod delay measurement. changed tq144 pinout for pins 34 and 35. 01/06/03 1.5 changed to preliminary, updated ac and dc specs per characterization review. updated note 5 on ac specifications from 10 ma to 13 ma at 3.6v. updated t pco (added t ptck ). updated ordering information format. 07/15/03 1.6 updated test conditions for i il and i ih . 08/21/03 1.7 updated package device marking pin 1 orientation.

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